This invention relates to semiconductor memory devices, and more particularly to an improved cell array structure for dynamic read/write memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynmic RAM) issued to White, McAdams, and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. Improvements in photolithography and semiconductor processing have made possible the 256K DRAM which is now available, and the 1-Megabit DRAM, now in development. All of these devices use a one-transistor storage cell in which the data is stored in a capacitor. In the devices of higher density, detecting the stored charge becomes more difficult because the cells are smaller and the bit lines longer, with more cells per bit line. A reliable signal cannot be detected by a differential sense amplifier when the ratio is less than about 1/30 or 1/40; preferably the ratio is in the area of 1/20 or less.
It is the principal object of this invention to provide improved high density dynamic RAM devices, particularly MOS devices using one-transistor cells. Another object is to provide a high density dynamic RAM in which the ratio of storage capacitance to bit line capacitance is a maximum.